In contrast to traditional planar metal-oxide-semiconductor, field-effect transistors (MOSFETs), which are fabricated using conventional lithographic fabrication methods, non-planar FETs incorporate various vertical transistor structures. One such semiconductor structure is the “FINFET”, which takes its name from the multiple semiconductor “fins” that are used to form the respective gate channels, and which are typically on the order of tens of nanometers in width. Advantageously, the fin structure helps to control current leakage through the transistor in the off stage, and a double gate or tri-gate structure may be employed to control short channel effects.
FIGS. 1A & 1B illustrate a top plan view and isometric view, respectively, of a typical FINFET 100. In the embodiment illustrated, FINFET 100 includes a gate 101 which is wrapped around the top and sides of a fin structure 103. A source 105 is formed at one end of fin structure 103, and a drain 107 is formed at the other end.
While FIGS. 1A & 1B depict a single FINFET, during FINFET fabrication a large number of fin structures are typically provided close together in a bulk process. After bulk fin formation, a fin cut or fin removal process may be employed to remove unwanted fin structures from the particular circuit or device being fabricated. As explained further herein, this fin cut processing can often leave unwanted fin residue, or result in excessive semiconductor removal.
Accordingly, a need exists for an enhanced fin cut process, for example, for use during FINFET device fabrication, which does not leave unwanted fin residue or result in excessive semiconductor removal.